1. Field of the Invention
The present invention relates to a thin film transistor array substrate and a method for manufacturing the same, and more particularly, to a thin film transistor array substrate for a liquid crystal display (LCD) and a method for manufacturing the same.
2. Descriptions of the Related Art
Evolution of associated technologies has led to continuous development of various display manufacturing technologies, for example, those using a planarization insulation layer. According to technologies using the planarization insulation layer, a photosensitive planarization insulation layer is formed prior to formation of a transparent electrode. The planarization insulation layer, which has a thickness generally greater than that of an insulation layer formed of silicon nitride or silicon oxide and a lower dielectric constant, provides both planarization functionality and a desirable insulation effect, which are detailed as follows.
Referring to FIGS. 1A and 1B together, FIG. 1A is a top view of a prior art thin film transistor (TFT) array substrate, and FIG. 1B is a schematic cross-sectional view of the prior art TFT array substrate. For convenience to reveal features of the prior art, FIG. 1A illustrates only some portions of the structure, and a more detailed structure of the TFT array substrate is shown in FIG. 1B. Additionally, these structures are shown in a single cross-sectional view and divided by separating lines into regions A-A′, B-B′ and C-C′ to depict cross-sectional structures along the section lines A-A′, B-B′ and C-C′ of FIG. 1. The TFT array substrate 1 comprises a substrate 10, on which a display area 11 (the area indicated by the section line A-A′) and a pad area 12 (the area surrounded by the dashed line) are defined. The pad area 12 further comprises a gate pad area 12a and a data pad area 12b (areas indicated by the section lines B-B′ and C-C′ respectively). A patterned first metal layer 13 disposed on the substrate 10 comprises a gate 131 disposed in the display area 11, a gate pad 132 disposed in the gate pad area 12a and a gate line 133 for connecting the gate 131 with the gate pad 132. A patterned first insulation layer 14 covers the substrate 10 and the patterned first metal layer 13. A patterned semiconductor layer 15 is disposed on the patterned first insulation layer 14 above the gate 131. A patterned second metal layer 16 is disposed on the patterned first insulation layer 14 in the display area 11, and covers portions of the patterned semiconductor layer 15. The patterned second metal layer 16 comprises a source 161 and a drain 162 disposed in the display area 11, a data pad 163 disposed in the data pad area 12b, and a data line 164 for connecting the source 161 with the data pad 163. All these connections are depicted in FIG. 1A. It should be appreciated that, the source 161 and the drain 162 are at least partially disposed on the patterned semiconductor layer 15 at two sides of the gate 131 respectively.
Further, a patterned second insulation layer 17 covers the display area 11, the gate pad area 12a and the data pad area 12b. It should be appreciated that, for convenience to draw a top view of FIG. 1B and for sake of description, the patterned second insulation layer 17 is omitted from depiction in FIG. 1A. Subsequently, a patterned planarization layer 18 is disposed on the patterned second insulation layer 17 in the display area 11.
FIG. 2 is a schematic view of the prior art TFT array substrate 1 using a half tone mask 24. During formation of the structure shown in FIG. 1B, through a photolithographic process using a half tone mask 24, openings 19′, 20′ and 21′ are formed in the planarization layer 18′. Afterwards, by using the planarization layer 18′ as a mask, the first insulation layer 14 and the second insulation layer 17 are etched to expose a portion of the drain 162 through a drain contact opening 19, and to expose a portion of the gate pad 132 and a portion of the data pad 163 through the first contact opening 20 and the second contact opening 21 respectively. Next, the planarization layer 18′ is removed from the pad area 12 and a pixel electrode 22 is formed on the patterned planarization layer 18 to cover the drain contact opening 19 for electrical connection with the drain 162. A pad conduction layer 23 covering the first contact opening 20 and the second contact opening 21 is formed to electrically connect with the gate pad 132 and the data pad 163, thus completing the structure shown in FIG. 1B.
Unfortunately, the aforesaid structure has the following disadvantages. If the residue of the patterned planarization layer 18 in the gate pad area 12a and the data pad area 12b has an overlarge thickness, conductivity between the pad conduction layer 23 and other components or conductive layers attached thereon, for example, conductivity between the pad conduction layer 23 and a driving integrated circuit (IC), will be affected. Moreover, use of the half tone mask has strict requirements on uniformity control of the photolithographic process, causing increased difficulty in mass production.
In view of above, it is highly desirable in the art to provide a TFT array substrate for an LCD that can make the manufacturing process smoother and lower the production cost.